The introduction of programmable logic devices (PLD) was a true revolution in the hardware design world. It enabled engineers to shrink circuits requiring several devices onto a single device thus simplifying their designs while saving space and power. Traditionally, PLDs have been used in combinational circuits such as address decoders as well as sequential circuits such as bus arbitration schemes. During the last few years, advances and improvements in PLD architectures enabled the devices to grow more complex while addressing the never-ending quest for higher density and faster speeds. Despite these improvements, engineers still face certain problems and limitations when implementing state machine designs with PLDSs.
A typical programmable logic device is composed of a user-programmable AND array, a fixed OR gate, followed by an output register which includes a feedback path from the output to the programmable AND array. Combination of these elements is commonly referred to as a `macrocell.` The existence of a feedback path from the output registers to the AND array makes PLDs ideal candidates for state machine implementations.
There are several basic categories of state machines such as Mealy and Moore machines. FIG. 1 illustrates the basics of a Mealy state machine as follows: a logic circuit 10, inputs 12 from the outside world, next state inputs 14, outputs 16, and outputs 18 leading to flip-flops 20.
The main characteristic of the Mealy is that its outputs 16, to the outside world, are a function of both inputs 12 and inputs 14. Inputs 14 couple the present state of the machine from flip-flops 20.
It is possible to implement any of the state machines in a PLD; however, there are inefficiencies in implementing state machines with current PLDs.
FIG. 2 illustrates that if a Mealy machine is implemented on a standard PLD, a wasteful two macrocells would be required--one per state register and one for each output. In operation, inputs 28, lead to both logic circuit 30 and 40, comprising an AND and OR matrix. Logic circuit 30 generates the next state then outputs to flipflops 32, working as memory elements. The outputs of register 32 is the current state, which is input to logic circuits 30 and 40. Logic circuit 40 has the current state and inputs 28 as inputs for decoding and then outputting over pads 44.
Inefficiencies occur in that pads 34 are by-passed and not used and that flip-flops 42 are likewise by-passed and not used. Specifically, both macrocell 33 and 43 are under-utilized.
The use of an extra macrocell is not an efficient use of the device resources and is fairly limiting in application. For example, generally a Mealy state machine with four outputs would be constrained to having no more than four state variables in an eight macrocell PLD.
Therefore, a need exists for an IC which has more efficient use of the macrocells, and specifically, the output pads and registers/flip-flops.